1. Field of the Invention
The present invention relates to a method and apparatus for communicating between components of a computer system and, more particularly, to a method and apparatus for communicating between multiple functional units of a central processing unit.
2. Related Art
A central processing unit or digital signal processor is the portion of a computer that receives and executes instructions. The term xe2x80x9cCPUxe2x80x9d as used herein will be defined to include both central processing units and digital signal processors. In modern desktop computers, the CPU is formed on a single chip of silicon and may be provided with a variety of functional units, each designed to perform a specific class of tasks, and on-chip memory. These functional units and memory communicate with each other over an internal bus. Communication over the internal bus takes place in a transaction. The internal bus of the CPU is connected via a bus interface unit (BIU) to an external bus so that other CPUs and peripheral devices, such as external memory, can issue transactions to access data or otherwise communicate with the functional units and memory within the CPU.
Since only one transaction can take place on the bus at one time, and since the internal bus is shared by many functional units, it is occasionally necessary to allow one functional unit to issue a transaction on the bus while denying another functional unit the right to issue a transaction on the bus. The process of determining which functional unit will have the right to issue a transaction on the bus is called arbitration. Numerous arbitration protocols have been developed for use in the arbitration process. The functional unit that wins the arbitration and is allowed to issue a transaction on the bus is called the bus master. A functional unit remains bus master until another functional unit successfully arbitrates mastership of the bus.
The rate at which data is transferred between functional units and memory of the CPU is often a limiting factor in the rate at which the CPU as a whole is able to execute instructions. To increase the data transfer rate, the size or speed of the bus may be increased, or the number of busses interconnecting the functional units and memory may be increased. If the number of busses is increased, the data transfer rate is increased by providing an increased number of paths over which data can be transferred as well as reducing the number of unsuccessful arbitrations.
Increasing the number or size of the internal busses, however increases the amount of space on the CPU""s chip that must be dedicated to implementation of the internal bus. Since space on the CPU chip is limited, minimizing the amount of space allocated to implementation of the internal bus is quite important. Accordingly, what is needed is a method and apparatus for increasing the data transfer rate between functional units and memory of a CPU that also minimizes the amount of space needed to implement the bus.
The present invention relates to a CPU having a number of functional units that cooperate together to execute instructions. On-chip memory is divided into several sections, each section of which is connected to one of a plurality of internal busses. All of the other functional units are connected to each of the internal busses so that each of the functional units can read from and write to all memory locations. When one of the functional units would like to access memory, it determines which memory location it requires, and then arbitrates for mastership of the bus associated with that section of on-chip memory. By providing two or more internal busses, two or more bus transactions can occur simultaneously.
Occasionally, the functional units will need to access another functional unit or a functional unit outside of the CPU. To minimize conflicts with internal memory transactions in this situation, the functional unit arbitrates for access of a virtual bus. The virtual bus includes a bus arbiter, but does not include a physical bus. Instead, the virtual bus arbiter monitors the internal busses or communicates with the other bus arbiters to determine which of the internal busses is unoccupied and, upon receiving a request to access the virtual bus, assigns one of the internal busses to the requesting functional unit. As used herein, the term xe2x80x9cvirtual busxe2x80x9d will be used to designate a bus arbiter without an associated physical bus. The specific protocol used by the virtual bus to allocate mastership of the physical busses will be discussed in greater detail below.
Using a virtual bus is advantageous for several reasons. First, since the virtual bus has information relating to use of the physical busses by other functional units, requesting access to the virtual bus has the affect of arbitrating for each of the physical busses simultaneously. Thus, the amount of time spent arbitrating for access to the physical busses is minimized. Second, since the physical busses typically do not run at 100% capacity, allocating use of the physical busses to non-memory transactions maximizes use of the physical busses without significantly distracting from the ability of the functional units to access memory. Finally, using a virtual bus instead of an additional physical bus takes up much less space on the chip. Accordingly, transactions between two or more functional units and between a functional unit and an outside resource can be accommodated without increasing the amount of space required for implementation of the internal bus while minimizing the amount of time wasted in arbitration.
In one embodiment, this invention is a processor including three physical busses, each associated with a bank of memory, and a virtual bus. A plurality of functional units are connected to each of the physical busses. Those functional units that are capable of initiating transactions on one of the physical busses are also connected to the virtual bus. In operation, when a functional unit would like to initiate a transaction with memory, the functional unit arbitrates for mastership of the bus associated with the bank of memory and, upon becoming bus master, completes its transaction. When a functional unit would like to initiate a transaction not involving memory, the functional unit arbitrates for mastership of the virtual bus and, upon becoming master of the virtual bus, completes its transaction.